ATMega644P SPI and SN74HC165 Shift Registers Example

Overview

The SNx4HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SNx4HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output. Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Because a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs. 

 

 

This input expansion chip can be used in Programmable Logic Controllers, Appliances, Video Display Systems, Keyboards etc. This old digital IC is very easy to use with a typical 8-bit MCU since it has a small footprint and its Dual In-Line Package version. It is widely available at very low cost.

A DIP-16 Sample

 It has DIP-16 footprint and various SMD packages.

 

Pin Configuration and Functions

 It made from some digital logic gates and flip-flops.

Logic Diagram Positive Logic

 To load parallel input data (H:A) take a look at the timing diagram below.

Load Shift Sequence

Typically the SI (Serial Data In) is ignored or wires it GND. The Clock Inhabit (CLK INH) must wired to GND. At the transition from logic low to logic high of SH/LD pin allows parallel data loading and serial data shifting out via Serial Data Out (SO) pin.

In this example the ATMega644P read parallel input data of an SN74HC165N and display it on PORTD.

Source Code "main.c":

1. /*
2. * 12-spi_sn74hc165.c
3. *
4. * Created: 2/16/2026 11:12:37 AM
5. * Author : Admin
6. */
7. 
   
8. #include <avr/io.h>
9. #include <util/delay.h>
10. #define F_CPU 16000000UL
11. 
    
12. #define DDR_SPI DDRB
13. #define PRT_SPI PORTB
14. 
    
15. #define DD_SS 4
16. #define DD_MOSI 5
17. #define DD_MISO 6
18. #define DD_SCK 7
19. 
    
20. 
    
21. void SPI_MasterInit(void)
22. {
23. /* Set MOSI and SCK output, all others input */
24. DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK)|(1<<DD_SS);
25. /* Enable SPI, Master, set clock rate fck/16 */
26. SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
27. }
28. 
    
29. void SPI_MasterTransmit(char cData)
30. {
31. /* Start transmission */
32. SPDR = cData;
33. /* Wait for transmission complete */
34. while(!(SPSR & (1<<SPIF)))
35. ;
36. }
37. 
    
38. void SPI_SlaveInit(void)
39. {
40. /* Set MISO output, all others input */
41. DDR_SPI = (1<<DD_MISO);
42. /* Enable SPI */
43. SPCR = (1<<SPE);
44. }
45. char SPI_SlaveReceive(void)
46. {
47. /* Wait for reception complete */
48. while(!(SPSR & (1<<SPIF)))
49. ;
50. /* Return Data Register */
51. return SPDR;
52. }
53. 
    
54. 
    
55. int main(void)
56. {
57. /* Replace with your application code */
58. SPI_MasterInit();
59. //PRT_SPI|=(1<<DD_SS);
60. DDRD=0xFF;
61. _delay_ms(1000);
63. while (1)
64. {
65. PRT_SPI&=~(1<<DD_SS);
66. PRT_SPI|=(1<<DD_SS);
67. SPI_MasterTransmit(0x00);
68. PORTD=SPI_SlaveReceive();
69. _delay_ms(100);
70. }
71. }
72. 
    
73. 
    
74. 
    

I don't have this chip because local stores don't stock this part. So I can test it only in simulator. 

 

SPI Transfer and Receive One Byte Of Data Waveform

We can connect multiple SN74HC165N chips using a daisy-chain configuration. Here I scan two input ports of two SN74HC165N. So the master MCU needs to shift 16 clock cycles (two bytes of data).

Using Two SN74HC165N chips (Daisy-Chain)

SPI Waveform

Source Code "main.c":

1. /*
2. * sn74hc165_2.c
3. *
4. * Created: 2/16/2026 12:49:13 PM
5. * Author : Admin
6. */
7. 
   
8. #include <avr/io.h>
9. #include <util/delay.h>
10. #define F_CPU 16000000UL
11. 
    
12. #define DDR_SPI DDRB
13. #define PRT_SPI PORTB
14. 
    
15. #define DD_SS 4
16. #define DD_MOSI 5
17. #define DD_MISO 6
18. #define DD_SCK 7
19. 
    
20. 
    
21. void SPI_MasterInit(void)
22. {
23. /* Set MOSI and SCK output, all others input */
24. DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK)|(1<<DD_SS);
25. /* Enable SPI, Master, set clock rate fck/16 */
26. SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
27. }
28. 
    
29. void SPI_MasterTransmit(char cData)
30. {
31. /* Start transmission */
32. SPDR = cData;
33. /* Wait for transmission complete */
34. while(!(SPSR & (1<<SPIF)))
35. ;
36. }
37. 
    
38. void SPI_SlaveInit(void)
39. {
40. /* Set MISO output, all others input */
41. DDR_SPI = (1<<DD_MISO);
42. /* Enable SPI */
43. SPCR = (1<<SPE);
44. }
45. char SPI_SlaveReceive(void)
46. {
47. /* Wait for reception complete */
48. while(!(SPSR & (1<<SPIF)))
49. ;
50. /* Return Data Register */
51. return SPDR;
52. }
53. 
    
54. 
    
55. int main(void)
56. {
57. /* Replace with your application code */
58. SPI_MasterInit();
59. //PRT_SPI|=(1<<DD_SS);
60. DDRD=0xFF;
61. DDRC=0xFF;
62. while (1)
63. {
64. PRT_SPI&=~(1<<DD_SS);
65. PRT_SPI|=(1<<DD_SS);
66. SPI_MasterTransmit(0x00);
67. PORTD=SPI_SlaveReceive();
68. SPI_MasterTransmit(0x00);
69. PORTC=SPI_SlaveReceive();
71. _delay_ms(100);
73. }
74. }
75. 
    
76. 
    
77. 
    

For PIC Micro-controller users check this post:

• PIC16F887 SPI and MCP23S17 XC8 Example 

For ATMega32 AVR micro-controller user check this post:

• ATMega32 SPI interfaces to 74HC165 and 74HC595 shift registers