ATMega644P SPI and 23K256 Serial SRAM

 Overview

The Microchip Technology Inc. 23X256 is a 256-Kbit Serial SRAM device. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. 

It supports clock rate up to 10MHz via its SPI interface. There many write and read modes, byte mode, page mode and sequential mode. Each pages contains 32 bytes of data.

 

This SPI chip does not have an address but it has some command before able read and write to this chip. Command or instruction locate at the first byte of data transmission. For example 0x03 for READ and 0x02 for WRITE.

Data read and write using byte mode

 By default this device operates in byte read or write mode.

ATMega644P and 23K256 Interfacing

To get start the master ATMega644P MCU write and read data from this chip using byte mode. SRAM data will display on PORTC.

Schematic

Source Code "main.c":

1. /*
2. * 12-spi_23K256.c
3. *
4. * Created: 2/25/2026 9:31:10 AM
5. * Author : Admin
6. */
7. 
   
8. #include <avr/io.h>
9. #include <util/delay.h>
10. #define F_CPU 16000000UL
11. 
    
12. #define DDR_SPI DDRB
13. #define PRT_SPI PORTB
14. 
    
15. #define DD_SS 4
16. #define DD_MOSI 5
17. #define DD_MISO 6
18. #define DD_SCK 7
19. 
    
20. void SPI_MasterInit(void)
21. {
22. /* Set MOSI and SCK output, all others input */
23. DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK)|(1<<DD_SS);
24. /* Enable SPI, Master, set clock rate fck/16 */
25. SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
26. }
27. 
    
28. void SPI_MasterTransmit(char cData)
29. {
30. /* Start transmission */
31. SPDR = cData;
32. /* Wait for transmission complete */
33. while(!(SPSR & (1<<SPIF)))
34. ;
35. }
36. 
    
37. void SPI_SlaveInit(void)
38. {
39. /* Set MISO output, all others input */
40. DDR_SPI = (1<<DD_MISO);
41. /* Enable SPI */
42. SPCR = (1<<SPE);
43. }
44. char SPI_SlaveReceive(void)
45. {
46. /* Wait for reception complete */
47. while(!(SPSR & (1<<SPIF)))
48. ;
49. /* Return Data Register */
50. return SPDR;
51. }
52. 
    
53. // 23K256 SPI SRAM
54. 
    
55. void write_bytes_23K256(unsigned int address, unsigned char data){
56. unsigned char temp;
57. PRT_SPI&=~(1<<DD_SS);
58. SPI_MasterTransmit(0x02);
59. SPI_MasterTransmit(address>>8);
60. SPI_MasterTransmit(address);
61. SPI_MasterTransmit(data);
62. PRT_SPI|=(1<<DD_SS);
63. }
64. 
    
65. unsigned char read_bytes_23K256(unsigned int address){
67. PRT_SPI&=~(1<<DD_SS);
68. SPI_MasterTransmit(0x03);
69. SPI_MasterTransmit(address>>8);
70. SPI_MasterTransmit(address);
71. SPI_MasterTransmit(0xFF);
72. unsigned char data=SPI_SlaveReceive();
73. PRT_SPI|=(1<<DD_SS);
74. return data;
75. }
76. int main(void)
77. {
78. /* Replace with your application code */
79. SPI_MasterInit();
80. PRT_SPI|=(1<<DD_SS);
81. unsigned char temp=0, data[16];
82. DDRC=0xFF;
83. while (1)
84. {
85. for (unsigned int i=0;i<8;i++)
86. {
87. write_bytes_23K256(i,1<<i);
88. PORTC=read_bytes_23K256(i);
89. _delay_ms(1000);
90. }
91. }
92. }
93. 
    
94. 
    
95. 
    
96. 
    
97. 
    
98. 
    

Now I put a character LCD to show data reading from the 23K256. This chip still operate in byte mode data read and write.

Schematic

 Source Code "main.c":

1. /*
2. * 23K256_1602.c
3. *
4. * Created: 2/25/2026 10:50:02 AM
5. * Author : Admin
6. */
7. 
   
8. #include <avr/io.h>
9. #include <util/delay.h>
10. #define F_CPU 16000000UL
11. 
    
12. #define DDR_SPI DDRB
13. #define PRT_SPI PORTB
14. 
    
15. #define DD_SS 4
16. #define DD_MOSI 5
17. #define DD_MISO 6
18. #define DD_SCK 7
19. 
    
20. void delay_1(unsigned int value){
21. for (unsigned int i=0;i<value;i++)
22. {
23. }
24. }
25. void SPI_MasterInit(void)
26. {
27. /* Set MOSI and SCK output, all others input */
28. DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK)|(1<<DD_SS);
29. /* Enable SPI, Master, set clock rate fck/16 */
30. SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
31. }
32. 
    
33. void SPI_MasterTransmit(char cData)
34. {
35. /* Start transmission */
36. SPDR = cData;
37. /* Wait for transmission complete */
38. while(!(SPSR & (1<<SPIF)))
39. ;
40. }
41. 
    
42. void SPI_SlaveInit(void)
43. {
44. /* Set MISO output, all others input */
45. DDR_SPI = (1<<DD_MISO);
46. /* Enable SPI */
47. SPCR = (1<<SPE);
48. }
49. char SPI_SlaveReceive(void)
50. {
51. /* Wait for reception complete */
52. while(!(SPSR & (1<<SPIF)))
53. ;
54. /* Return Data Register */
55. return SPDR;
56. }
57. 
    
58. // 23K256 SPI SRAM
59. 
    
60. void write_bytes_23K256(unsigned int address, unsigned char data){
62. unsigned char temp;
63. PRT_SPI&=~(1<<DD_SS);
64. SPI_MasterTransmit(0x02);
65. SPI_MasterTransmit(address>>8);
66. SPI_MasterTransmit(address);
67. SPI_MasterTransmit(data);
68. PRT_SPI|=(1<<DD_SS);
69. //delay_1(1000);
70. }
71. 
    
72. unsigned char read_bytes_23K256(unsigned int address){
73. PRT_SPI&=~(1<<DD_SS);
74. SPI_MasterTransmit(0x03);
75. SPI_MasterTransmit(address>>8);
76. SPI_MasterTransmit(address);
77. SPI_MasterTransmit(0xFF);
78. //delay_1(1000);
79. unsigned char data=SPI_SlaveReceive();
80. PRT_SPI|=(1<<DD_SS);
81. return data;
82. }
83. int main(void)
84. {
85. /* Replace with your application code */
86. _delay_ms(50);
87. SPI_MasterInit();
88. PRT_SPI|=(1<<DD_SS);
89. unsigned char temp=0, data[16];
90. lcd_init();
91. lcd_clear();
92. lcd_text("ATMega644P SRAM");
93. lcd_xy(1,2);
94. lcd_text("Serial 23K256");
95. _delay_ms(10000);
96. lcd_clear();
98. for (unsigned int i=0;i<10;i++)
99. {
100. write_bytes_23K256(i,'0'+i);
101. }
102. for (unsigned int i=0;i<10;i++)
103. {
104. lcd_data(read_bytes_23K256(i));
105. }
107. lcd_xy(1,2);
108. for (unsigned int i=0;i<16;i++)
109. {
110. write_bytes_23K256(i+10,'A'+i);
111. }
112. for (unsigned int i=0;i<16;i++)
113. {
114. lcd_data(read_bytes_23K256(i+10));
115. }
116. while (1)
117. {
119. }
120. }
121. 
     

The LCD drivers are not here you can download this project package in download section below. I tested it on my AVR ATMega644P prototype board. It works fine and fast. But the wires connection problem between the prototype board and the bread board often cause problems to data communication.

 

Using sequential writing and reading mode could save processing time. However the master MCU must put the 23K256 to operate in this mode by writing an instruction to this chip.

Read Status Register Instruction

 The schematic is shown in previous example. The LCD shows the result of data reading from SRAM.

Source Code "main.c":

1. /*
2. * 23K256_Sequential_1602.c
3. *
4. * Created: 2/25/2026 2:37:30 PM
5. * Author : Admin
6. */
7. 
   
8. #include <avr/io.h>
9. #include <util/delay.h>
10. #define F_CPU 16000000UL
11. #include <stdio.h>
12. 
    
13. #define DDR_SPI DDRB
14. #define PRT_SPI PORTB
15. 
    
16. #define DD_SS 4
17. #define DD_MOSI 5
18. #define DD_MISO 6
19. #define DD_SCK 7
20. 
    
21. void delay_1(unsigned int value){
22. for (unsigned int i=0;i<value;i++)
23. {
24. }
25. }
26. void SPI_MasterInit(void)
27. {
28. /* Set MOSI and SCK output, all others input */
29. DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK)|(1<<DD_SS);
30. /* Enable SPI, Master, set clock rate fck/16 */
31. SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
32. }
33. 
    
34. void SPI_MasterTransmit(char cData)
35. {
36. /* Start transmission */
37. SPDR = cData;
38. /* Wait for transmission complete */
39. while(!(SPSR & (1<<SPIF)))
40. ;
41. }
42. 
    
43. void SPI_SlaveInit(void)
44. {
45. /* Set MISO output, all others input */
46. DDR_SPI = (1<<DD_MISO);
47. /* Enable SPI */
48. SPCR = (1<<SPE);
49. }
50. char SPI_SlaveReceive(void)
51. {
52. /* Wait for reception complete */
53. while(!(SPSR & (1<<SPIF)))
54. ;
55. /* Return Data Register */
56. return SPDR;
57. }
58. 
    
59. // 23K256 SPI SRAM
60. 
    
61. void write_bytes_23K256(unsigned int address, unsigned char data){
63. unsigned char temp;
64. PRT_SPI&=~(1<<DD_SS);
65. SPI_MasterTransmit(0x02);
66. SPI_MasterTransmit(address>>8);
67. SPI_MasterTransmit(address);
68. SPI_MasterTransmit(data);
69. PRT_SPI|=(1<<DD_SS);
70. }
71. 
    
72. unsigned char read_bytes_23K256(unsigned int address){
73. PRT_SPI&=~(1<<DD_SS);
74. SPI_MasterTransmit(0x03);
75. SPI_MasterTransmit(address>>8);
76. SPI_MasterTransmit(address);
77. SPI_MasterTransmit(0xFF);
78. unsigned char data=SPI_SlaveReceive();
79. PRT_SPI|=(1<<DD_SS);
80. return data;
81. }
82. 
    
83. void write_sequential_23K256(unsigned int address, unsigned char *data){
84. PRT_SPI&=~(1<<DD_SS);
85. SPI_MasterTransmit(0x01);
86. SPI_MasterTransmit(1<<6);
87. PRT_SPI|=(1<<DD_SS);
89. unsigned char temp;
90. PRT_SPI&=~(1<<DD_SS);
91. SPI_MasterTransmit(0x02);
92. SPI_MasterTransmit(address>>8);
93. SPI_MasterTransmit(address);
94. while(*data) { SPI_MasterTransmit(*data++); delay_1(10);}
95. PRT_SPI|=(1<<DD_SS);
96. }
97. 
    
98. unsigned char data_read[32];
99. void read_sequential_23K256(unsigned int address,unsigned int size){
100. PRT_SPI&=~(1<<DD_SS);
101. SPI_MasterTransmit(0x01);
102. SPI_MasterTransmit(1<<6);
103. PRT_SPI|=(1<<DD_SS);
105. unsigned char *temp;
106. PRT_SPI&=~(1<<DD_SS);
107. SPI_MasterTransmit(0x03);
108. SPI_MasterTransmit(address>>8);
109. SPI_MasterTransmit(address);
110. for (unsigned int i=0;i<size;i++)
111. {
112. SPI_MasterTransmit(0xFF);
113. data_read[i]=SPI_SlaveReceive();
114. delay_1(10);
115. }
116. PRT_SPI|=(1<<DD_SS);
117. }
118. 
     
119. int main(void)
120. {
121. /* Replace with your application code */
122. _delay_ms(500);
123. SPI_MasterInit();
124. PRT_SPI|=(1<<DD_SS);
125. 
     
126. lcd_init();
127. lcd_clear();
129. while (1)
130. {
132. lcd_xy(1,1);
133. write_sequential_23K256(0,"ATMEGA644P SPI");
134. for (unsigned int i=0;i<14;i++)
135. {
136. data_read[i]=read_bytes_23K256(i);
137. }
138. lcd_text(data_read);
139. write_sequential_23K256(16,"23K256 SRAM ");
140. lcd_xy(1,2);
141. read_sequential_23K256(16,16);
142. lcd_text(data_read);
143. _delay_ms(10000);
144. lcd_clear();
146. write_sequential_23K256(32,"ABCDEFGHIJKLMOPQ");
147. lcd_xy(1,1);
148. read_sequential_23K256(32,16);
149. lcd_text(data_read);
150. write_sequential_23K256(64,"RSTUVWXYZ !@#$%^");
151. lcd_xy(1,2);
152. read_sequential_23K256(64,16);
153. lcd_text(data_read);
154. _delay_ms(10000);
155. lcd_clear();
157. }
158. }
159. 
     

I tested it on AVR ATMega644P Prototype Board. There are some unwanted data on SRAM space. So the master MCU must clear them first.

 

Click here to download this example.