ATMega644P SPI SN74HC595N TC1604A LCD

The SN74HC595N is an output expansion chip that could drive any devices, LED, relay or even writing data to LCD. A character LCD is easily controlled by this chip in write mode. A single chip SN74HC595N can control the HD44780 using its 4-bit data transfer mode.

 

 

 

In this example the ATMega644P master SPI send HD44780 LCD data and command to the LCD via an SN74HC595N shift registers chip.

A finished Assembling. SN74HC595N is soldered on-board. A 16x4 LCD stays at the top.

 

Soldering side

 

Schematic Diagram

 The original post uses Arduino Uno to control this LCD module.

Source Code "main.c":

1. /*
2. * 12-spi_74hc595_1604.c
3. *
4. * Created: 2/17/2026 3:27:49 PM
5. * Author : Admin
6. */
7. 
   
8. #include <stdio.h>
9. #include <avr/io.h>
10. #include <util/delay.h>
11. #define F_CPU 16000000UL
12. 
    
13. #define DDR_SPI DDRB
14. #define PRT_SPI PORTB
15. #define DD_MOSI 5
16. #define DD_MISO 6
17. #define DD_SCK 7
18. #define DD_SS 4
19. 
    
20. void SPI_MasterInit(void)
21. {
22. /* Set MOSI and SCK output, all others input */
23. DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK)|(1<<DD_SS);
24. /* Enable SPI, Master, set clock rate fck/16
25. data is sample at the falling edge of SCK*/
26. SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
27. }
28. 
    
29. void SPI_MasterTransmit(char cData)
30. {
31. /* Start transmission */
32. SPDR = cData;
33. /* Wait for transmission complete */
34. while(!(SPSR & (1<<SPIF)))
35. ;
36. }
37. 
    
38. void SPI_SlaveInit(void)
39. {
40. /* Set MISO output, all others input */
41. DDR_SPI = (1<<DD_MISO);
42. /* Enable SPI */
43. SPCR = (1<<SPE);
44. }
45. 
    
46. char SPI_SlaveReceive(void)
47. {
48. /* Wait for reception complete */
49. while(!(SPSR & (1<<SPIF)))
50. ;
51. /* Return Data Register */
52. return SPDR;
53. }
54. 
    
55. /*TWI LCD Driver*/
56. #define RS 1
57. #define RW 2
58. #define EN 3
59. #define BL 0
60. 
    
61. 
    
62. char backLight=0;
63. 
    
64. void lcd_delay(unsigned int counts){
65. for (unsigned int i=0;i<counts;i++);
66. }
67. 
    
68. void spi_lcd_command(char command){
69. char data;
70. data=command&0xF0;
71. SPI_MasterTransmit(data|(backLight<<BL)|(1<<EN));
72. PRT_SPI&=~(1<<DD_SS);
73. PRT_SPI|=(1<<DD_SS);
75. SPI_MasterTransmit(data|(backLight<<BL));
76. PRT_SPI&=~(1<<DD_SS);
77. PRT_SPI|=(1<<DD_SS);
79. data=command<<4;
80. SPI_MasterTransmit(data|(backLight<<BL)|(1<<EN));
81. PRT_SPI&=~(1<<DD_SS);
82. lcd_delay(10);
83. PRT_SPI|=(1<<DD_SS);
84. SPI_MasterTransmit(data|(backLight<<BL));
85. PRT_SPI&=~(1<<DD_SS);
86. PRT_SPI|=(1<<DD_SS);
87. }
88. 
    
89. void spi_lcd_data(char command){
90. char data;
91. data=command&0xF0;
92. SPI_MasterTransmit(data|(backLight<<BL)|(1<<EN)|(1<<RS));
93. PRT_SPI&=~(1<<DD_SS);
94. PRT_SPI|=(1<<DD_SS);
95. SPI_MasterTransmit(data|(backLight<<BL)|(1<<RS));
96. PRT_SPI&=~(1<<DD_SS);
97. PRT_SPI|=(1<<DD_SS);
98. lcd_delay(50);
100. data=command<<4;
101. SPI_MasterTransmit(data|(backLight<<BL)|(1<<EN)|(1<<RS));
102. PRT_SPI&=~(1<<DD_SS);
103. PRT_SPI|=(1<<DD_SS);
104. SPI_MasterTransmit(data|(backLight<<BL)|(1<<RS));
105. PRT_SPI&=~(1<<DD_SS);
106. PRT_SPI|=(1<<DD_SS);
107. }
108. 
     
109. void spi_lcd_xy(int8_t x, int8_t y){
110. //16x2
111. //char addr[]={0x80,0xC0};
112. //16x4
113. char addr[]={0x80,0xC0,0x90,0xD0};
114. spi_lcd_command(addr[y-1]+x-1);
115. }
116. 
     
117. void spi_lcd_line_1(void){
118. spi_lcd_command(0x80);
119. }
120. 
     
121. void spi_lcd_line_2(void){
122. spi_lcd_command(0xC0);
123. }
124. 
     
125. void spi_lcd_line_3(void){
126. spi_lcd_command(0x90);
127. }
128. 
     
129. void spi_lcd_line_4(void){
130. spi_lcd_command(0xD0);
131. }
132. 
     
133. void spi_lcd_cursor_off(void){
134. spi_lcd_command(0x0C);
135. }
136. 
     
137. void spi_lcd_text(char *txt){
138. while(*txt) spi_lcd_data(*txt++);
139. }
140. 
     
141. void i2c_lcdClear(void){
142. spi_lcd_command(0x01);
143. _delay_ms(10);
144. }
145. 
     
146. void spi_lcd_init(void){
148. SPI_MasterTransmit(0);
149. lcd_delay(500);
150. spi_lcd_command(0x33);
151. lcd_delay(10);
152. spi_lcd_command(0x32);
153. lcd_delay(10);
154. spi_lcd_command(0x28);
155. lcd_delay(10);
156. spi_lcd_command(0x0F);
157. lcd_delay(10);
158. spi_lcd_command(0x01);
159. _delay_ms(10);
160. spi_lcd_command(0x06);
161. lcd_delay(10);
162. }
163. 
     
164. int main(void)
165. {
166. /* Replace with your application code */
167. _delay_ms(1000);
168. SPI_MasterInit();
169. PRT_SPI|=(1<<DD_SS); //Set CS Pin High
170. spi_lcd_init();
171. spi_lcd_line_1();
172. spi_lcd_text("ATMega644P SPI");
173. spi_lcd_line_2();
174. spi_lcd_text("SN74HC595N LCD");
175. spi_lcd_line_3();
176. spi_lcd_text("TC1604A-01(R)");
177. spi_lcd_line_4();
178. spi_lcd_text("Example Using C");
179. unsigned char data[7],msg[16];
180. while (1)
181. {
183. }
184. }
185. 
     
186. 
     
187. 
     
188. 
     

AVR Hardware Experiment:

Tested ATMega644P

For a full tutorial list of ATMega644P using C in Microchip Studio IDE please see this page.

 

 

ATMega644P SPI DS3234 RTC LCD

Overview

The DS3234 is a low-cost, extremely accurate SPI bus real-time clock (RTC) with an integrated temperature-compensated crystal oscillator (TCXO) and crystal. The DS3234 incorporates a precision, temperature-compensated voltage reference and comparator circuit to monitor VCC. When VCC drops below the power-fail voltage (VPF), the device asserts the RST output and also disables read and write access to the part when VCC drops below both VPF and VBAT. The RST pin is monitored as a push button input for generating a µP reset. The device switches to the backup supply input and maintains accurate timekeeping when main power to the device is interrupted. The integration of the crystal resonator enhances the long-term accuracy of the device as well as reduces the piece-part count in a manufacturing line. The DS3234 is available in commercial and industrial temperature ranges, and is offered in an industry-standard 300-mil, 20-pin SO package. 

It does not have a DIP version due to larger footprint. But a ready to use module is widely available at very low cost. 

Its internal time keeping and general purpose registers are similar to the DS1307 and almost identical to DS3232 (TWI version). However its SPI interface yield a higher speed data communication than TWI.

DS3234 Pin Configuration and Description

 Its timing data is very precise due its internal 32.678KHz crystal oscillator with programmable capacitors array.

Block Diagram

The DS3234 provides 256 bytes of general-purpose battery-backed read/write memory. The SRAM can be written or read whenever VCC is above either VPF or VBAT.  

 Address Map for DS3234 Timekeeping Registers and SRAM

This SPI chip doesn't have a device address. It just uses a Chip Select (CS) pin that is active low. Its R/W MSB bit of the internal SRAM address identifies between device write and read( '0' for read and '1' for write).

DS3234 Single-Byte Write and Read Sequence

 However for a high speed multiple write or read bytes we can use its SPI mutliple-Byte Burst Transfer.

SPI Multiple-Byte Burst Transfer

 It is very common for data reading from this chip.

ATMega644P and DS3234 Interfacing

Programming and interfacing with this chip is very easy using a simple 8-bit MCU dedicated SPI communication module. Even a low-end 8-bit micro-controller that doesn't have an SPI communication interface the programmer can emulate an SPI communication protocol to interact with this RTC chip. 

Typical Operating Circuit

Commonly a master MCU uses only four wire SPI to make a bi-directional communication interface with this RTC chip.

Proteus Simulation

 

Virtual DSO Waveform

 

In this example the ATMega644P read the time and date data from the SRAM of DS3234. A character LCD show time and date on the display. Serial data inputs to MISO pin are sample at the trailing edge of each clock cycles of SCK pin to correct the data reception that is CPOL=0 and CPHA=1.

C Source Code "main.c":

/*
 * 12-spi_ds3234_1602.c
 *
 * Created: 2/16/2026 10:52:32 PM
 * Author : Admin
 */ 

#include <stdio.h>
#include <avr/io.h>
#include <util/delay.h>
#define F_CPU 16000000UL

#define DDR_SPI DDRB
#define PRT_SPI PORTB
#define DD_MOSI 5
#define DD_MISO 6
#define DD_SCK 7
#define DD_SS 4

void SPI_MasterInit(void)
{
	/* Set MOSI and SCK output, all others input */
	DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK)|(1<<DD_SS);
	/* Enable SPI, Master, set clock rate fck/16 
		data is sample at the falling edge of SCK*/
	SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0)|(1<<CPHA);
}

void SPI_MasterTransmit(char cData)
{
	/* Start transmission */
	SPDR = cData;
	/* Wait for transmission complete */
	while(!(SPSR & (1<<SPIF)))
	;
}

void SPI_SlaveInit(void)
{
	/* Set MISO output, all others input */
	DDR_SPI = (1<<DD_MISO);
	/* Enable SPI */
	SPCR = (1<<SPE);
}

char SPI_SlaveReceive(void)
{
	/* Wait for reception complete */
	while(!(SPSR & (1<<SPIF)))
	;
	/* Return Data Register */
	return SPDR;
}

int main(void)
{
	/* Replace with your application code */
	SPI_MasterInit();
	PRT_SPI|=(1<<DD_SS); //Set CS Pin High	
	
	lcd_init();
	lcd_text("ATMega644P AVR");
	lcd_xy(1,2);
	lcd_text("DS3234 SPI RTC");
	_delay_ms(5000);
	lcd_command(0x0C);
	unsigned char data[7],msg[16];
	while (1)
	{	
		PRT_SPI&=~(1<<DD_SS);	
		SPI_MasterTransmit(0x00);	
		for (char i=0;i<7;i++)
		{
			SPI_MasterTransmit(0x00);		
			data[i]=SPDR;
		}
		PRT_SPI|=(1<<DD_SS);
		sprintf(msg,"Date: 20%02X/%02X/%02X",data[6],data[5],data[4]);
		lcd_xy(1,1);
		lcd_text(msg);
		sprintf(msg,"Time: %02X:%02X:%02X",data[2],data[1],data[0]);
		lcd_xy(1,2);
		lcd_text(msg);
		_delay_ms(100);
	}
}

I can not buy this chip at local store. So I only tested this SPI RTC chip using a software simulator. 

 

 

 

 

ATMega644P SPI and SN74HC165 Shift Registers Example

Overview

The SNx4HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SNx4HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output. Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Because a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs. 

 

 

This input expansion chip can be used in Programmable Logic Controllers, Appliances, Video Display Systems, Keyboards etc. This old digital IC is very easy to use with a typical 8-bit MCU since it has a small footprint and its Dual In-Line Package version. It is widely available at very low cost.

A DIP-16 Sample

 It has DIP-16 footprint and various SMD packages.

 

Pin Configuration and Functions

 It made from some digital logic gates and flip-flops.

Logic Diagram Positive Logic

 To load parallel input data (H:A) take a look at the timing diagram below.

Load Shift Sequence

Typically the SI (Serial Data In) is ignored or wires it GND. The Clock Inhabit (CLK INH) must wired to GND. At the transition from logic low to logic high of SH/LD pin allows parallel data loading and serial data shifting out via Serial Data Out (SO) pin.

In this example the ATMega644P read parallel input data of an SN74HC165N and display it on PORTD.

Source Code "main.c":

1. /*
2. * 12-spi_sn74hc165.c
3. *
4. * Created: 2/16/2026 11:12:37 AM
5. * Author : Admin
6. */
7. 
   
8. #include <avr/io.h>
9. #include <util/delay.h>
10. #define F_CPU 16000000UL
11. 
    
12. #define DDR_SPI DDRB
13. #define PRT_SPI PORTB
14. 
    
15. #define DD_SS 4
16. #define DD_MOSI 5
17. #define DD_MISO 6
18. #define DD_SCK 7
19. 
    
20. 
    
21. void SPI_MasterInit(void)
22. {
23. /* Set MOSI and SCK output, all others input */
24. DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK)|(1<<DD_SS);
25. /* Enable SPI, Master, set clock rate fck/16 */
26. SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
27. }
28. 
    
29. void SPI_MasterTransmit(char cData)
30. {
31. /* Start transmission */
32. SPDR = cData;
33. /* Wait for transmission complete */
34. while(!(SPSR & (1<<SPIF)))
35. ;
36. }
37. 
    
38. void SPI_SlaveInit(void)
39. {
40. /* Set MISO output, all others input */
41. DDR_SPI = (1<<DD_MISO);
42. /* Enable SPI */
43. SPCR = (1<<SPE);
44. }
45. char SPI_SlaveReceive(void)
46. {
47. /* Wait for reception complete */
48. while(!(SPSR & (1<<SPIF)))
49. ;
50. /* Return Data Register */
51. return SPDR;
52. }
53. 
    
54. 
    
55. int main(void)
56. {
57. /* Replace with your application code */
58. SPI_MasterInit();
59. //PRT_SPI|=(1<<DD_SS);
60. DDRD=0xFF;
61. _delay_ms(1000);
63. while (1)
64. {
65. PRT_SPI&=~(1<<DD_SS);
66. PRT_SPI|=(1<<DD_SS);
67. SPI_MasterTransmit(0x00);
68. PORTD=SPI_SlaveReceive();
69. _delay_ms(100);
70. }
71. }
72. 
    
73. 
    
74. 
    

I don't have this chip because local stores don't stock this part. So I can test it only in simulator. 

 

SPI Transfer and Receive One Byte Of Data Waveform

We can connect multiple SN74HC165N chips using a daisy-chain configuration. Here I scan two input ports of two SN74HC165N. So the master MCU needs to shift 16 clock cycles (two bytes of data).

Using Two SN74HC165N chips (Daisy-Chain)

SPI Waveform

Source Code "main.c":

1. /*
2. * sn74hc165_2.c
3. *
4. * Created: 2/16/2026 12:49:13 PM
5. * Author : Admin
6. */
7. 
   
8. #include <avr/io.h>
9. #include <util/delay.h>
10. #define F_CPU 16000000UL
11. 
    
12. #define DDR_SPI DDRB
13. #define PRT_SPI PORTB
14. 
    
15. #define DD_SS 4
16. #define DD_MOSI 5
17. #define DD_MISO 6
18. #define DD_SCK 7
19. 
    
20. 
    
21. void SPI_MasterInit(void)
22. {
23. /* Set MOSI and SCK output, all others input */
24. DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK)|(1<<DD_SS);
25. /* Enable SPI, Master, set clock rate fck/16 */
26. SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
27. }
28. 
    
29. void SPI_MasterTransmit(char cData)
30. {
31. /* Start transmission */
32. SPDR = cData;
33. /* Wait for transmission complete */
34. while(!(SPSR & (1<<SPIF)))
35. ;
36. }
37. 
    
38. void SPI_SlaveInit(void)
39. {
40. /* Set MISO output, all others input */
41. DDR_SPI = (1<<DD_MISO);
42. /* Enable SPI */
43. SPCR = (1<<SPE);
44. }
45. char SPI_SlaveReceive(void)
46. {
47. /* Wait for reception complete */
48. while(!(SPSR & (1<<SPIF)))
49. ;
50. /* Return Data Register */
51. return SPDR;
52. }
53. 
    
54. 
    
55. int main(void)
56. {
57. /* Replace with your application code */
58. SPI_MasterInit();
59. //PRT_SPI|=(1<<DD_SS);
60. DDRD=0xFF;
61. DDRC=0xFF;
62. while (1)
63. {
64. PRT_SPI&=~(1<<DD_SS);
65. PRT_SPI|=(1<<DD_SS);
66. SPI_MasterTransmit(0x00);
67. PORTD=SPI_SlaveReceive();
68. SPI_MasterTransmit(0x00);
69. PORTC=SPI_SlaveReceive();
71. _delay_ms(100);
73. }
74. }
75. 
    
76. 
    
77. 
    

For PIC Micro-controller users check this post:

• PIC16F887 SPI and MCP23S17 XC8 Example 

For ATMega32 AVR micro-controller user check this post:

• ATMega32 SPI interfaces to 74HC165 and 74HC595 shift registers