Using Digital I/O of PIC18F1220

 

Introduction

PIC18F1220 has two 8-bit digital I/O ports – Port A and Port B. They are bi-directional readable and writable. Their data directions are controlled by their TRIS registers.

Port A

Port A data direction is controlled by TRISA. Setting this registers allowing this port to accept input data, otherwise outputting digital data.

PORTA is considered as an input buffer. LATA is an output buffer. These two registers must be cleared before configuring its data direction.

Pin diagram of PIC18F1220

Port B

Port B data direction is controlled by TRISB. Setting this register allowing this port to accept input data, otherwise outputting digital data.

PORTB is considered as an input buffer. LATB is an output buffer. These two registers must be cleared before configuring its data direction.

Port B Programming Example

Since Port A and Port B are multiplexed with analog input function. I decided to select some pin of Port B that are solely digital I/O pin.

Schematic Diagram

RB6 of Port B is selected as a digital input pin connecting to a push button. RB7 connects to an output LED. Whenever push button is pressed the controller toggle output LED.

Schematic Diagram

External crystal oscillator has a frequency of 4MHz.

MPLABX XC8 Programming

This introductory tutorial is written in XC8 in MPLABX IDE. Overall program made of a dozen of lines.

C

/*

 * PIC18F1220 digital I/O Reading

 */

#include <xc.h>

#include "config.h"

​

#define SW1     RB6

#define LED1    RB7

​

void main(void){

    /*Clear I/O*/

    LATB=0x00;

    PORTB=0x00;

    /*RB6 digital input*/

    TRISB=0x40;

    while(1){

        /*Check input status*/

        if(RB6==1){

            /*Wait until SW1 released*/

            while(RB6==1);

            /*Toggle LED1*/

            LATB^=0x80;

        }

    }

}

Configuration bit of PIC18F1220 putted separately in “config.h” file.

C

// PIC18F1220 Configuration Bit Settings

​

// CONFIG1H

#pragma config OSC = XT         // Oscillator Selection bits (XT Oscillator)

#pragma config FSCM = ON        // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor enabled)

#pragma config IESO = ON        // Internal External Switchover bit (Internal External Switchover mode enabled)

​

// CONFIG2L

#pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)

#pragma config BOR = ON         // Brown-out Reset Enable bit (Brown-out Reset enabled)

// BORV = No Setting

​

// CONFIG2H

#pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))

#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)

​

// CONFIG3H

#pragma config MCLRE = ON       // MCLR Pin Enable bit (MCLR pin enabled, RA5 input pin disabled)

​

// CONFIG4L

#pragma config STVR = ON        // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)

#pragma config LVP = OFF        // Low-Voltage ICSP Enable bit (Low-Voltage ICSP disabled)

​

// CONFIG5L

#pragma config CP0 = OFF        // Code Protection bit (Block 0 (00200-0007FFh) not code-protected)

#pragma config CP1 = OFF        // Code Protection bit (Block 1 (000800-000FFFh) not code-protected)

​

// CONFIG5H

#pragma config CPB = OFF        // Boot Block Code Protection bit (Boot Block (000000-0001FFh) not code-protected)

#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)

​

// CONFIG6L

#pragma config WRT0 = OFF       // Write Protection bit (Block 0 (00200-0007FFh) not write-protected)

#pragma config WRT1 = OFF       // Write Protection bit (Block 1 (000800-000FFFh) not write-protected)

​

// CONFIG6H

#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)

#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot Block (000000-0001FFh) not write-protected)

#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

​

// CONFIG7L

#pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (00200-0007FFh) not protected from table reads executed in other blocks)

#pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (000800-000FFFh) not protected from table reads executed in other blocks)

​

// CONFIG7H

#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot Block (000000-0001FFh) not protected from table reads executed in other blocks)

​

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